This evening I had a few minutes to implement the next IPC improvement I had in mind. This one is just implementing the simple end of instruction pipeline for instructions where it is possible, the same as I have already done for single byte instructions, and the same as what the real 6502 has always done.
The result is a nice little speed up as the pictures show.
This is among the last of the speed ups that I will do before a substantial reimplementation of the CPU to make it table driven. Using a table reduces the FPGA logic consumption a lot, and also has the potential to allow the CPU speed to be increased quite a bit, hopefully to 64MHz or even 96MHz all going well. But it is really the logic reduction that matters, so that I have space to implement the missing features in the C65GS.