Sunday, December 14, 2014

RAM Upgrade

Someone has just pointed out to me that he Nexys4 board that the C65GS project is based on is about to receive a modest upgrade in the form of switching from the 16MB cellular RAM to a 128MB DDR2 RAM module:

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,1301,1319&Prod=NEXYS4DDR

Reading through the new reference manual for the Nexys4 DDR, I discover the following:

The Nexys4 DDR is an incremental update to the Nexys4 board. The major improvement is the replacement of the 16 MiB CellularRAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that wraps the complexity of a DDR2 controller and is backwards compatible with the asynchronous SRAM interface of the CellularRAM, with certain limitations. See the Nexys4 DDR page at www.digilentinc.com for updates.
Furthermore, to accommodate the new memory, the pin-out of the FPGA banks has changed as well. The constraints file of existing projects will need to be updated. 
The audio output (AUD_PWM) needs to be driven open-drain as opposed to push-pull on the Nexys4.
So overall the changes look relatively small, and it shouldn't be hard to port the design to the new board.

The actual DDR2 memory part is a MT47H64M16HR-25:H, which is capable of 667MB/sec, but according to the reference manual the practical limit will be 650MHz.  Xilinx have a memory interface generator which should make it fairly easy to interface to this RAM, although DDR memory is inherently more complex.

I will likely implement a very small cache, perhaps 8 or 16 bytes, because although the DDR2 RAM has a bandwidth of 650MB/sec, the random-access latency of DDR memory is typically fairly high, and it will be important to avoid incurring this latency on every slowram memory access.

Taking a quick look at the data sheet for the DDR RAM, it looks like the actual speed is 650MT/sec, i.e., 650 mega-transactions per second. I have done some reading on DDR and DDR2 RAM lately, but will need to sit down with the actual memory specifications to work out what this all means in practice.

What is almost certain is that the DDR2 RAM could drive a linear frame buffer if I wanted to, but as I have discussed on the mailing list, a linear frame buffer doesn't fit my definition of an 8-bit style computer.  However, there is already 128MB of address space already reserved for slowram expansion, so it will be quite straight-forward to incorporate it.

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