I have managed to get the C65GS to synthesise targetting the new Nexys4DDR board, however there are still some big problems to solve.
First, here is the hypervisor trying to load the kernal ROM. Now that we have a new lab at work, I have a new way to get decent analog screen-shots, by simply taking a picture of the wall-mounted 60" flat-screen. It also makes for a very big cursor :)
Back to the technical bits.
On the plus side, it can see the SD card, and can read from it, so that side of things is all working nicely. However, it is going through the cluster numbers one at a time, because it thinks that I have a physical switch on the FPGA board set to the debug position, which I don't.
Taking a look at the board, I can see that clearly the pinout on the FPGA isn't what I think it is, as the segmented leds are doing odd things, and those two super-bright LEDs shouldn't be trying to beam light to the moon. The green indicator LEDs look like they are wired up properly, though, so that's a plus.
I let it go through the slow debug-mode loading of the ROM, to see if I could get it to think that the debug switch had been released. While the debug switch is set, it won't actually boot.
Unfortuntely, I couldn't.
A bit of digging in the serial monitor confirmed that the pinout, or something else is wrong, as watching $D6F0/$D6F1 for the switch positions showed no change when moving the switches.
Supporting the idea that the pinout is all mixed up, I did see that one of the switches gets interpreted as one of the directional buttons on the FPGA board.
It was thus no surprise to find that the DDR memory was also not being responsive, since it is also likely to have messed up pin assignments.
On the positive side, the DDR controller synthesised, and the system seems to be mostly working, apart from these issues.
Now my challenge is to find out why the pinouts are all messed up, given that I copied the new pin assignments from Digilent's demo project for the Nexys4DDR2 board. I might have to confirm the schematic with them.