I continue to pull my hair out with the DDR controller -- but it does seem that I have fixed the bug that would cause the DDR controller to lock up forever until a reset. It still doesn't always write a byte when asked, but even those events are now <1% of the time. With the lock up bug fixed, I might be able to re-enable infinite write retries in the CPU state machine, and make writing appear reliable. So this is good progress.
Meanwhile, I have been working on the Hypervisor upgrade process, and have that all nicely working now. On cold-start, the hypervisor checks for KICKUP.G65, and if present, loads it and replaces itself with the contents of that file, it then sets the one-time "hypervisor upgraded" hardware flag, and jumps into the entry point of the new hypervisor, which seeing that flag, knows not to try to upgrade itself. I guess I could have also had it do a checksum and if the new and current version are identical, to just continue without replacing itself, but I didn't think of that until later :/
So now the main barriers to actually getting it working on the DDR board is to make writing reliable, and fix a new little (but very important) bug with DDR writing, which causes the next CPU instruction fetch to read from DDR memory instead of from whatever it should have been reading from. Hopefully once this is fixed, I might finally be out of the woods and able to run the C65 and C64 ROMs again. I will feel a lot better once I reach that point.