Monday 17 April 2017

Prototype MEGA65 PCBs at Revision 2017

This weekend many of the MEGA65 team are at the Revision 2017 demo party.

Excitingly, they have with them the first prototype PCBs for the MEGA65 mainboard, thanks to Antti's amazing work.

So, before we get any further, it is time for some pictures.

First, here is the bare PCB before being populated:

Then with just the bare minimum components for initial testing by Antti:

Having real hardware, even if it is 18,000km away from me was a very exciting moment!

However, excitement had to give way to hard work, if we wanted the MEGA65 to actually run on the new PCB during the party.

First step, update the mega65-core repository to add a branch (m65pcb) with a target for the new board, and work out all the pin assignments.  That process took longer than I would have liked, but after a day or so, we had kickstart running, and the new 24-bit VGA output working.

The Nexys4 boards have only 12-bit VGA output, so I decided to make a quick routine to draw a vertical colour gradient by writing the contents of $D012 (current VIC-II raster line) into $D100 (red channel of palette entry 0).  It was pleasing (via skype video call) to see this all working.

Then the next step was to solder on a microSD slot to a set of test pads.  The final PCBs will of course have a microSD slot on them, but the time crunch for revision meant that these first prototypes didn't.  Fortunately, the PMOD connectors also aren't wired up, so it was possible for the guys to use a PMOD microSD adapter, and link the test pads to the appropriate pins.

Note that in the above image an incompatible SDHC card is visible. We're still working on adding SDHC support.  After switching it for a 2GB SD card, and putting the appropriate files on there, the familiar C65 boot screen appeared.  No photo of that, because if you are reading this, you probably already know what it looks like.

What I didn't mention above, was that after some initial problems with the VGA output, we realised the VDAC chip on these prototypes is only rated to a 170MHz dotclock.  The MEGA65 currently is still using a 1200p 60Hz video mode, with a dotclock of 193MHz.  As a result, the VDAC was not happy, and there was no image.  Solution: lie to the VDAC and claim our dotclock is only half what it really is. Result: it samples only every other pixel, which makes the horizontal non-integer scaling in 80 column mode look uglier than normal.  This will of course be fixed for future PCBs.

Then we found some problems with the keyboard interface. Basically there is cross-talk of some sort, or possibly weak pull-ups in the FPGA not allowing lines to float back high quickly enough.  This causes some strange problems with phantom keys being pressed:

However, these problems are when we are using real C65 keyboards with the PCB.  Needless to say, this is a very nice step forward in usability and authentic feel.

Time constraints also meant that the joystick ports lacked pull-ups (they are on separate lines from the keyboard, so that we can make MEGA65 software work more happily with keyboard + joysticks simultaneously).  Antti confirmed that with pull-ups, we can read those lines just fine.  Hopefully we will be able to update the bitstream soon to enable them before the end of the party.

 Speaking of bitstreams, we are loading the bitstreams onto a 32MB SPI flash on the PCB.  We can set this to configure the FPGA on power-on at 66MHz and 4-bit parallel, for a total 33MB/sec. As the bitstream is ~9MB, this gives a power-on time of 0.25 - 0.3 seconds -- very nice.

Finally, we have some of the folks celebrating and presenting the PCBs at the party:

Sunday 2 April 2017

Emulating an 8080 on the MEGA65

I must say I was very impressed to discover what LGB has been up to lately:

As the URL suggests, he has been working towards CP/M emulation on the MEGA65.

What is remarkable is that he is currently obtaining the performance of an approximately 12MHz 8080 CPU on the MEGA65, i.e., about 3x faster than many of the real CP/M computers -- but this is emulation using the 45GS10 CPU of the MEGA65 to achieve this.  Put another way: The 45GS10 can emulate an 8080 at fully 1/3 of the clock speed of the 45GS10.  

Both he and I were at first rather surprised that it could emulate at such speed.  However, on inspection, it turns out that the 45GS10 is quite friendly for emulating foreign hardware.  Specifically, the combination of a large address space, together with the ZP-indirect 32-bit addressing mode and the JMP ($nnnn,X) jump-table instruction means that an emulator can operate in its own address space, separate from the emulated system, and use ZP registers as emulated registers, with the ZP-indirect 32-bit mode allowing dereferencing of those emulated registers.