But, as I say, it is now possible to run the DDR board just fine, booting to C65 BASIC and everything. This means I should be able to live with out a "Don't ask me about the DDR controller" T-Shirt.
The solution is that I am using almost every last spare bit of BRAM in the FPGA to have a 128KB "ROM" in the design, instead of storing the C65 ROM in DDR RAM. This has three main effects for now:
1. The "ROM" is now zero wait state, and as a result BASIC and the DOS routines fly. They are about 6x to 8x faster than they were previously. The C65's horribly slow DOS routines can load somewhere around 50 - 100 blocks per second. You can also do FORI=1TO25000:NEXTI in about 1 second in C64 mode, i.e., around 50x faster than on a stock C64. In fact, BASIC is now so fast that you can use POKE to change the border colour about every 5 or 6 C64 raster lines.
2. I was planning to use the BRAM for enhanced sprites. Clearly that can't happen now. I am thinking about how to feed sprites direct from DDR RAM, which would be fun.
3. The "ROM" is of course really RAM. The Hypervisor can make it read-only for compatibility with any of the very few C65 programs that exist, if any happen to try writing over the ROM address space. But for C65GS specific programs you can of course just use it as an extra 128KB of RAM. I'll do another post about this soon, describing all of the RAM that is usefully available on the C65GS for programmers.