Sadly not pretty pictures right now, but I am actively working on fixing the C65-mode bitplanes. This largely consists of making some changes to work out how far the data is getting through the pipeline, resynthesising, and then repeating until I find where the bitplane data is reaching the bit bucket. What I know so far, is that bitplane mode turns on, and that the bitplane complement bits work just fine. It just seems that the bitplane feeders are either not activating when they should, or that they just receive (or just output) all zeroes.
Of course this debug process means I sit around waiting 1 - 2 hours for synthesis sometimes, so in those gaps I am implementing GeoRAM and REU emulation. These turn out to be not that hard to do. GeoRAM is just trivial to implement, because of its super-cheap design. The REU is also fairly easy to implement because its functions are quite easily mapped to the C65's DMAgic. So I am just implementing it as a special front-end to the DMAgic interface in the CPU. The only new feature to add here is the verify mode of the REU, which DMAgic lacks. So it is quite likely that I will have these two RAM expansion controllers working fairly soon -- of course it would then be REALLY nice to have the 128MB DDR2 RAM working, so that they can be usefully used.
In any case, the hypervisor will be able to control the size of each RAM expansion, and point them to the same or different places anywhere in the full 28-bit address space. This means that you will be able to do weird things like point the REU expansion memory to the C64-mode 64KB of RAM, or to colour RAM, or to any other weird location you might choose.