I have finally found and fixed the problem that was stopping most (but not all) CIA IRQs in the redesigned CPU. The result was the cursor would blink very slowly.
I had bashed away for several days on the CIA, to try to figure out what was going wrong, with no luck. I wasn't able to reproduce the problem in simulation, so I was pulling my hair out.
So I progressively added more and more instrumentation that revealed that the CIA was resetting the interrupt status register, and that it seemed to be doing so at the request of the CPU. This should only happen if the CPU is reading from $DC0D.
It was about then that the realisation dawned on me that because the memory controller on my CPU has separate channels for RAM, IO and other types of memory, it is possible for the IO bus to still be presenting the instruction to read from the last accessed IO address. Indeed $DC0D is the last IO address touched in the C64's IRQ routine, and thus the problem.
This also explains why the problem would go away if I accessed any IO-mapped memory, even from the serial monitor. In retrospect, I should probably have reflected on this a little more deeper, especially the fact that the CIA design hadn't changed, but my CPU design HAD changed since it was last all working.
Anyway, this was a reminder of why hardware design is hard: it does exactly what you ask it, and keeps on doing it until you ask it to stop. Getting that right all of the time takes a lot of careful attention and testing.