So I have replaced these simple integer counters with fixed point counters that are used as divisors for the width of pixels. A value of 1 means that logical pixels will be 128 pixels wide, while a value of 255 means that logical pixels will be 1/2 a physical pixel wide. This allows zoom factors from 0.5x to 128x, with very fine granularity at the smaller end of the range. The following frame shows the smaller end of the range and just how fine the graduation is. You really need to click on the image and zoom it in to see what is going on. Memory is not uniformly initialised, hence the different textures that can be seen.
There is no sub-pixel sampling, so there will be aliasing effects. Nonetheless, the result is much more flexible than it was previously. When I get a moment I will adjust the 80-column display modes to use this with 2.5 physical pixels per logical pixel, so that the borders don't move when switching to 80 column mode -- unless of course the result looks too silly with the mix of fat and skinny pixels.
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ReplyDeletePrevious comment removed for bad english...
DeleteGreat work ! I visit here almost daily to follow your progress :)
If I only had the expertise/skill to help :(
Keine Probleme -- Ich wette, Ihr Englisch ist bessere als mein Deutsch.
DeleteAnyway, glad you are enjoying the blog.
Also, people assume that VHDL is impossible to learn. However, if you can do 6502 assembly, then you can learn it quite easily I think - it is all about thinking about cycles, timing and moving bits around the place.
I've built and programmed a single board Z80 computer: perhaps there's some hope for me to learn some FPGA too :)
DeleteHave you got some advice about some books, and a good developement board ?
What are you exactly using for your project ?
Is something a noob can try to use in order to learn ?
I am using a Nexys4 board, which is the only board out there at the moment that can run the C65GS, as it contains one of the quite new 7-series FPGAs from Xilinx. There are a few VHDL tutorials out there, the learning curve is a little steep, but not insurmountable. Persistence is the key as with learning anything new. You could get a cheaper littler board to learn on. I would recommend something with VGA out and some sort of keyboard input, because then you can do interesting things fairly easily. Email me and I will try to get you some more specific stuff.
DeletePaul.
You've got mail :)
DeleteThanks Paul.
Danke schön, ich wird lesen es nun.
DeleteGreat work Paul. Probably some kind of simple filtering isn't too much work if you already got this far. Maybe a line based as would be suitable in this case. Or would it introduced too high bandwidth somehow?
ReplyDeleteHi Magnus,
DeleteIt is probably possible to do some horizontal filtering, but any subsampling approach will require too much bandwidth if done while drawing the raster, since it is one cycle per pixel. That said, it could be done as an extra pipeline stage in the raster buffer collecting perhaps. That method would use the known zoom factor to read the pixels and add them in a collector register like a bucket, and then output the average value when the bucket fills. The problem is the fractional apportioning of the logical pixels when they span two (or more) physical pixels.
It isn't a high priority right now, but of course if someone wrote this little piece in VHDL, it would be easy to insert.
I really need to just get the sd card controller working again, so that it can load the ROM and work through the remaining CPU bugs so that it boots properly again. It is so close, and yet still not there right now.
Paul.