Friday 3 April 2020

Misleading ERROR: [Synth 8-2396] from Vivado SOLVED

This short post is really one for the folks out there pulling their hair out with FPGA development in general, rather than the MEGA65 specifically.

I have had errors like the following a few times, and it always takes me a while to remember what the cause is:

ERROR: [Synth 8-2396] near character '1' ; 3 visible types match here

The reason it takes me a while to remember the cause, is that all the information out there doesn't really explain what has gone wrong, and Vivado produces this error instead of, say, actually reporting the real problem, which is that you are using an entity or component, without declaring it in your project_gen.tcl file. 

Without the declaration, Vivado doesn't know what type the field is that you are assigning something innocent like a '1' or a '0' to, and thus throws this error.  So I understand HOW Vivado produces such a misleading error, but it still really is a royal pain.

And here's a random picture of an FPGA board, since if I don't have one, it messes up some of the places we push this blog to :)


  1. Where is this project_gen.tcl file

    1. That will depend on your project. In the MEGA65 source tree, this is in the vivado/ sub-directory, but it could be anywhere in other projects. If on linux, you can try something like: find . -iname project_gen.tcl