Well, we thought we had the R4 board all settled, and then the ghost of supply chains past came back to visit, requiring some changes to the R4 board to accommodate the lack of availability of one of the voltage regulators.
This is giving us the opportunity to make some further minor refinements based on feedback from our community, to make the cartridge port compatible with more cartridges. This is because in the previous PCB revisions, I didn't realise that we needed to have the /RESET, /GAME, /EXROM, /IRQ, /NMI and potentially also /ROML and /ROMH lines should be bi-directional.
This requires one additional FPGA pin for each of these lines, but there are currently no spare pins, so we need a way to save 7 pins.
We can do this by replacing the 4 FPGA pins that are used to identify board revisions (but was only added on the R4 board), and the 4 FPGA pins used to connect to the DIP switches with an I2C IO expander. This would require only 2 pins (and allow 8 DIP switches instead of 4, which would be handy), thus saving 6 pins. We can then re-use DBG10 for the 7th one, thus meeting our needs.
To make this change we would need to:
0. The revised board shall be called R5, because it will not be bitstream compatible with R4, and is not feature identical, because of the cartridge port enhancements that will result from these changes.
1. Remove the CHS-04TA dipswitch, freeing FPGA pins N18, P19, T16 and U16.
2. Remove the REV_BIT0 - REV_BIT3 assignments, freeing FPGA pins L15, M16, F20 and T21.
3. Add a PCA9555 or similar 16-bit I2C IO expander with internal pull-up resistors (or alternatively, a PCA9535 or similar that lacks pull-up resistors, and then add external pull-up resistors as required to the signals described in (4) - (6).
4. Assign REV_BIT0 -- REV_BIT3 to 4 IO pins on the IO expander, to indicate REV5, i.e., with BIT1,3 tied to GND, and BIT0,2 unconnected to float to VCC.
5. Create new SUBREV_BIT0 -- SUBREV_BIT3 to indicate the sub-revision of the board, to indicate sub-revision 0 = "R5" without suffix letter, i.e., BIT0,1,2,3 tied to GND.
6. Add an 8-position dipswitch (or 2x8 pin 0.1" male header such as this to save cost), connected to the other 8 IO pins of the I2C IO expander.
7. Connect the I2C interface of IO expander to FPGA pins N18 and P19.
8. Disconnect F_C64_ROMH, F_C64_ROML, C64_ROMH and C64_ROML from U8.
9. Add an NC7SZ126P5X IC (similar to U30) to input and level shift C64_ROMH to F_C64_ROMH, but with pin 1 (OE, active high) connected to new signal F_C64_ROMH_DIR.
10. Add an NC7SZ126P5X IC (similar to U30) to input and level shift C64_ROML to F_C64_ROML, but with pin 1 (OE, active high) connected to new signal F_C64_ROML_DIR.
11. Add a 74AHCT1G125DBV gate to allow driving C64_ROMH low when new signal F_C64_ROMH_DIR is low, with pin 2 of the gate tied to existing signal F_C64_ROMH, to create a tri-stateable output driver, pulled high by the existing C64_ROMH pull-up resistor R99.
12. Assign the new signal F_C64_ROMH_DIR to FPGA pin T16.
13. Add a 74AHCT1G125DBV gate to allow driving C64_ROML low controlled by the new signal F_C64_ROML_DIR and existing signal F_C64_ROML, similar to (11).
14. Assign the new signal F_C64_ROML_DIR to FPGA pin U16.
15. Disconnect F_C64_RESET and C64_RESET from U9.
16. Add an NC7SZ126P5X IC (similar to U30) to level input and level shift C64_RESET to F_C64_RESET, but with pin 1 (OE, active high) connected to new signal F_C64_RESET_EN.
17. Add a 74AHCT1G125DBV gate to allow driving C64_RESET low controlled by the new signal F_C64_RESET_EN, similar to U30.
18. Assign the new signal F_C64_RESET_EN to FPGA pin T21.
19. Add a 74AHCT1G125DBV gate to allow driving C64_GAME low controlled by the new signal F_C64_GAME_EN and existing signal F_C64_GAME, similar to U30.
20. Assign the new signal F_C64_GAME_EN to FPGA pin L15.
21. Add a 74AHCT1G125DBV gate to allow driving C64_EXROM low controlled by the new signal F_C64_EXROM_EN and existing signal F_C64_EXROM, similar to U30.
22. Assign the new signal F_C64_EXROM_EN to FPGA pin M16.
23. Add a 74AHCT1G125DBV gate to allow driving C64_NMI low independently, controlled by the new signal F_C64_NMI_EN and existing signal F_C64_NMI, similar to U30.
24. Assign the new signal F_C64_NMI_EN signal to FPGA pin F20.
25. Add a 74AHCT1G125DBV gate to allow driving C64_IRQ low independently, controlled by the signal DBG10 on pin 1 of the gate, and existing signal F_C64_IRQ on pin 2 of the gate, similar to U30.
26. Replace R41 and R42 with 3.3K resistors instead of the current 4.7K resistors. This will then exactly match the value of those on the C64.
That list looks long, but all it really does is fix those seven signals to be independently bidirectionally controllable at high-speed. When I say high-speed, I mean at full cartridge speed of ~2MHz. The routing on the PCB can, however, be as byzantine as is expedient, because they are still very low speed in the grand scheme of things.
The next step is to submit this to Trenz Electronic, so that they can sanity check it for us, and confirm if the changes are feasible.