In the last blog post, I got the tape port working, which was nice. Now to get the user port working, and also deal with a number of other bits and pieces that need attacking.
First, I have added de-coupling capacitors to all the ICs in the schematic and PCB design, since they should be used, even though I have tested the board fine without them.
Anyway, let's get testing the user port data lines... and nothing shows up. At least one problem was that the CIA data direction register is active high, while the expansion board uses active-low. So I have fixed that, which requires a resynthesis. With that, I am able to set the data lines. To test reading them I really need a user port connector so that I can rig up a switch or something. But in the absence of that I am probing the lines using a jumper wire, and I can see the input value change, but because of the lack of pull-ups it's a bit wonky, because once the lines are left floating they can settle on whatever they like. But it looks like they work.
The other lines that I need to test are:
RESET (output and input)
ATN (output)
PA2 (output and input)
CNT1 (output and input)
SP1 (output and input)
CNT2 (output and input)
SP2 (output and input)
PC2 (output)
FLAG2 (input)
Starting with the RESET line, this one is a bit tricky because it's bi-directional: We want the MEGA65 to pull it low when the system is reset, but we also want external devices to be able to trigger reset by pulling it low. The trouble comes because the reset line isn't really connected to the reset line of the MEGA65, so we have to fake it, and know when we are faking pulling it low, so that we know not to read it. This also has to handle the latency of the expansion board controller. So the logic looks something like this:
-- Export RESET generated by MEGA65 to the userport
user_port_o.reset <= reset;
-- But when doing so, ignore the RESET pin's value on the
-- user port, as otherwise once reset were triggered, you
-- wouldn't be able to release it.
-- Because of the latency of the user port reading, we need
-- to remember that /RESET has been asserted for a while.
-- User port scans at a rate of ~150KHz, so at 40.5MHz this means we need
-- to remember it for ~270 cycles. We'll do 1,000 to be sure
if reset='1' then
if cycles_since_reset = 1000 then
reset_out_user_port <= user_port_i.reset_n;
else
cycles_since_reset <= cycles_since_reset + 1;
reset_out_user_port <= '1';
end if;
else
cycles_since_reset <= 0;
reset_out_user_port <= '1';
end if;
reset_out <= reset_out_keyboard and reset_out_user_port;
That'll need a resynthesis to test, as will the ATN line, that needs to be connected to the IEC ATN signal from the CIA. I could also connect it to the ATN line of the hardware IEC accelerator that is being added to the MEGA65, but it doesn't really make sense, since the rest of the IEC lines are not exposed on the user port, and it would be a bit of a pain in the bum to plumb it through. So instead, the user port ATN line will just follow the CIA line for it.
Okay, resynthesis is done, and the RESET pin works in both directions: If you hold the reset button on the MEGA65, /RESET on the user port goes to 0V, and if you temporarily ground /RESET on the user port, the MEGA65 resets -- and then when you release it, it continues to boot as it should -- so that fancy logic works... provided the expansion board is fitted.
The ATN line works, but has reversed sense, so I'll have to fix that: Done and confirmed fixed.
The trouble is that I don't have 2 spare outputs, only 1. What I will do to work around that, is make PA2 open-collector instead of CMOS push-pull logic. For 99% of use-cases that shouldn't matter. I've updated the schematic and PCB design, as well as the VHDL. On my prototype I will just need to connect the following 2 pins:
U6 pin 3 to U9 pin 4
They look pretty easy to patch, so I'll do that while the VHDL synthesises.
Ok, in theory both are now done. I can now control PA2 from the CIA, so that's good. And I can still read it, so that's PA2 all done and dusted.
So RESET, ATN and PA2 are all good now.
PC2 is a pain: It's supposed to be a strobe whenever port B of the CIA is read or written. The trick is, if we hold it only for 1 cycle, then our relatively slow expansion board bus will miss the strobe. Actually, looking at our CIA implementation, we currently strobe it only for 1 cycle at 40.5MHz, rather than 1 cycle at 1MHz. Nothing else in the MEGA65 uses it, so I'll just make the CIA make the strobe last longer than the 33 phases x 10 cycles that the expansion board bus takes. So 330 should be enough, but we'll make it 511 to be on the safe side. That'll need a synthesis run before I can test it -- which it does.
The remaining 5 lines: CNT1, CNT2, SP1, SP2 and /FLAG are a bit more of a pain to test, as they require more sophisticated programming of the CIA. Also, for CNT and SP, these are the lines most likely to hit problems with the relatively slow update rate of the user port lines on the expansion port: The CIA can shift data at 250KHz or faster, but the ring bus on the expansion board is currently clocking only around 150KHz. So I'm just going to settle for a verification of the electrical connectivity of these lines, to back up the VHDL simulation based testing I did previously.
The same is going to have to suffice for the C1565 connector, as I can't find the replica drive board I have here somewhere, and don't have time right now to reverse-engineer and make a new board. Everything looks fine there.
In short, I have now tested all that I can test for the moment of the IO lines on expansion board, and am confident that the remaining lines work correctly at an electrical level, even if I can't confirm the VHDL to drive them is correct yet.
So now it's a bit of a home-run effort to square up a few miscellaneous things, in no particular order.
First, this revision of the board should have 3 channels on the analog video output. Again for now, I just want to be sure that they are on the correct pins, and are electrically working. Yes: Probing the appropriate pins of the video connector, I can see video signals. Again, for the moment I don't care if the video signals are correct, but rather whether the wiring is all correct, as this was wrong on the previous board revision.
Next, I need to confirm that the floppy drive and cable can fit in with the board. This was also a bit snug on the previous revision, so there is a bit more space on this revision to fit the cable in. That's what the funny cut-out below U6 and U7 is for:
Otherwise, the last change to make on the board before I do send that off is to correct the position of the holes in the MEGA65 case. This is a bit fiddly to get right. It's easy after you get a PCB to see that it's wrong, and roughly by how much. But getting any degree of precision is much harder, as is making sure you have made all the movements in the correct directions. A good approach is to print a piece of paper with the hole positions, and then compare it to the case. A challenge for me with this is that our printer likes to scale things without asking, so it's hard to get a true 1:1 printout. After 5 test prints, I have converged on a scale factor of 1.0425:1 in KiCad's print dialog to get it pretty much exactly 1:1. So now I can make changes, do a print, and then compare it to the case. What would be even better would be if I had access to a laser cutter, as I could cut a piece of paper to have holes in it where the screw holes should be to make it super easy to compare. If necessary, I'll be able to use a power drill and 3mm bit to approximate this.
But first, let's get those holes in the right place, and also add the missing hole. I have pretty good measurements from the case now for their relative positions. One factor is getting the distance from the back of case to the first row of holes right, so that it positions well. I'm going to deem that hole H9 is in the correct location, and adjust everything from that.
I believe I have the holes right now, so time to attack a sheet of paper with a power drill, and see how well the holes actually line up. By sandwiching the paper between a block of wood and a blank expansion board PCB, so that one of the 3mm holes in the PCB lined up with the black circle on the paper where a hole should be, I was able to quite cleanly and accurately drill out the holes in the print-out of the PCB, and then fit-test it:
Fit testing just consisted of making sure I could see into the screw boss holes in the case through the holes in the paper, like this:
Pleasingly all the holes were correct on the first attempt :)
I've also increased the thickness of the 5V tracks to 1mm everywhere, and branched the 3.3V and 5V rails as much as I could, to minimise voltage drop. I am also tempted to see if I can possibly route the JTAG header to be closer to the MEGA65 board, so that a simple bridging PCB could be used instead of a cable for that, too. But I'm not sure if the PCB might not already be too congested.. and it turned out to be possible. This is how it looks now:
So in theory at least, the revised PCB is now ready for fabrication again. But as I mentioned, I want to also make a simple connector PCB that can join the PMODs on the MEGA65 to the connectors on the expansion board.
But first, that PMOD bridging PCB. The PMOD connectors should be 77.5mm apart, and it just needs to connect all the pins 1:1, without any re-ordering. We can add a GND and 3.3V plane and make it a 4 layer PCB, so that we only need to route the data lines. This is what the little board looks like:
The board is totally passive, as it just needs to connect the MEGA65 main board and the expansion board. It's only ~150x10mm, so it should also be quite cheap to make. The notch on one of the lower corners is the corner that will be exposed in the trap-door slot near the SD card, so I removed the corner so you don't poke yourself on it when changing SD cards.
Well, I had hoped to get the PCBs ordered today, but its got late, and I've only just managed to finish the PCB designs, so that will have to wait until tomorrow, but I should just be able to export the gerber files and place the order with PCBway.
It's tomorrow, and among a bunch of errands I had to run, I decided to make a 3rd PCB that can be used in place of all the remaining cables to connect the expansion board to the MEGA65 main board, so that everything is neater and tidier:
The 3 connectors on the left connect to the appropriate headers on the MEGA65, and the other three to the expansion board. It was quite tricky to get the connectors into exactly the right relative positions, as I don't have a super accurate layout of the MEGA65 board, and the relative positioning of the MEGA65 board to the expansion board also has a bit of slop in it. So I will just get some samples made, and then correct any position errors after. Hopefully there won't be any significant errors, as I did do the trick of printing the PCB out and laying it over to make sure the drill holes all line up -- as best I can without having actual connectors attached.
It was a bit of extra effort to design this up, and try to get the positions right, but I think it will be worth it, because the cables are all a pain to work with, while this should make it quite trivial to connect everything together. In short, you won't have to have the inside of your MEGA65 look like this rat's nest -- which is good, because I can't actually close the case while all those cables are there!
So hopefully I will finally actually place the PCB order tomorrow, and then work out what components I need to be able to assemble. In particular, I don't think I have 34-pin female headers on hand. But I'll have a poke around in the shed in the morning.
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