Okay, now that we have the overall design of the MEGAphone laid out, we can start drilling down into the individual modules. We'll start with the first one on the list:
High-efficiency DC:DC converter
1. Requirements Analysis
But start with the requirement list for this module, which is pretty straight-forward:
Requirement 1.4.1: High-efficiency DC switchable DC power supplies that can support various sub-systems with >=2A @ 3.3V or 5V (externally selectable), with an efficiency of at least 90% in typical conditions when powered from a single cell LiFEPO4 battery (28.V - 3.2V).
So it must be:
1. Switchable (ie we can turn it on and off)
2. >=2A @ 3.3V or 5V
3. Externally selectable between 3.3V and 5V output.
4. Efficiency >= 90% in typical conditions
5. Can be powered from a single LiFEPO4 battery (2.8V -- 3.2V typical range, but can be up to 3.7V fully charged).
2. Selection of Key Component(s)
Looking at my previous blog post, I've suggested to myself that the following part
is likely to be a good option, specifically the ISL91127IRAZ, which is adjustable voltage:
https://www.renesas.com/en/document/dst/isl91127ir-datasheet
As the goal here is for an MVP, we are less fussed with whether this will be the absolute best/cheapest/most efficient part, and more concerned about making a working module as quickly as possible. They are about US$7 each singly, which is not fantastic, but we'll live with it for now.
Here's their typical application schematic for the variable voltage output, which is the one we want:
The efficiency curve with 3.3V input looks good. It will be a bit worse with lower voltage, but overall it looks good, only dropping below 90% for very low or very high current draws, in particular at lower input voltages. But given that we have a working input voltage range of ~2.6V to 3.6V, this keeps us in the >=90% efficiency zone.
It has an EN pin to enable/disable it, which meets sub-requirement 1.
The datasheet indicates 2A output, which meets sub-requirement 2.
The variable-voltage mode supports output voltages from 1V to 5.2V, which meets sub-requirement 3.
The efficiency is >=90% across the working input voltage range, which meets sub-requirement 4.
So the input range is fine, which meets sub-requirement 5.
In short, we are now satisfied that this part meets the requirements.
3. Module Design: Module External Interfaces
A module hosting this unit will require the following external interfaces:
1. GND plane as input.
2. V_BAT as input.
3. EN line as control signal (V_BAT vs 0V).
4. Output voltage select line (tie to GND for 3.3V, leave floating for 5V)
5. V_OUT
So not many pins.
4 Module Design: Voltage Selection Logic
I'm designing this, so that I can avoid the need to populate a resistor on the carrier board. My goal is to have a common R1 for both voltages, and then an R2 connected to each of the 3.3V and 5V select lines. The carrier board then ties the desired voltage to GND, and leaves the other select pin floating. The other alternative is to have one of them always connected to GND, and then have a single voltage select pin that connects another resistor in parallel to the other, causing the alternate voltage to be selected.
Having one voltage selection resistor always active should prevent the situation where the feedback line can go open-circuit, which might result in a higher voltage being output.
In terms of resistor selection for this, let's see what the datasheet has to say about the typical resistor values. I'm assuming fairly high values, so that we don't waste too much energy. This is reinforced by their advice here:
When designing a PCB, include a GND guard band around the
feedback resistor network to reduce noise and improve accuracy
and stability. Resistors R1 and R2 should be positioned close to
the FB pin.
This suggests to me that this circuit will be quite high-impedence, and thus prone to noise.
For 5V output, our waste current will be 5V / (R1+R2), so to keep waste current below 1mA, we would need R1+R5 >= 5K. That feels very comfortable. Having them around 50K would get us down to 100 micro Amps, which is even better, without going to crazy impedance levels. But we could even go a decade higher, given the datasheet talks about R1=1Mohm. So let's aim for around there.
Now let's look at the difference in resistor ratio that we need for 3.3V vs 5V, to see if we can't use the same value resistor for everything here, to simplify the BoM.
So the equation to solve for is VOUT = 0.8 * (1 + R1/R2).
To get 3.3V we need 1+R1 / R2 = 4.125 and for 5V we need 6.25. Remove the 1 term, and those reduce to 3.125 and 5.25. Now, those aren't too crazy fractions, but just annoying enough that having arrays of identical value resistors would be a pain.
So let's fall back to working out some resistor value ratios that would allow us to have an R2A that is always tied to GND, and an R2B that is tied to GND only when you want 3.3V.
So R2A = R1 / 5.25, which is the easy part. R2B isn't too hard, but we have to use the parallel resistor equation: R2 = 1 / ( 1/R2A + 1/R2B). I could try to solve this numerically, but it's easier to just whack it into a spreadsheet, and fiddle with the numbers until they are right.
Ratios of R1 : R2A : R2B = 29 : 9 : 14 yields output voltages of 3.38V and 5.03V, which feels reasonable. So let's try putting some real resistor values in for these, and see how close to ideal voltages we can get.
R1 : R2A : R2B = 291000 : 92000 : 138000 looks pretty good, with output voltages of 3.33V and 5.02V.
What's also nice about this from a failure mode perspective, is if the R2B ground strap fails, then R2 increases, which decreases the R1/R2 the ratio, which in turn decreases the voltage. That is, a dry joint or failure in this manner results in the safer option of the voltage dropping, rather than increasing.
Let's now look at the other passives:
C1 is a fixed 10 uF X5R type, with the recommendation to have two of them.
C2 is a fixed 22uF X5R type, again with the recommendation to have two of them.
C3 is more interesting: It's recommended at 56pF for R1=1M Ohm. This kind of feedback circuit is not something I'm super familiar with, but some chatting with ChatGPT suggests that C3 should be proportional to the inverse of R1. So if we are going to use R1=291K, then C3 should be 56pF x (1M / 291K) = 192pF, NPO type.
L1 should be 1uH, >=4A saturation current.
5. Module Design: Part Selection
Let's look at some possible part numbers for these:
C1 - CL21A106KOQNNNG. Also massively stocked. 0805 SMD, which is fine. They are plausibly hand-solderable, but given the DC:DC converter IC with its thermal pad on the underside are a bastard to hand-solder, this is one of the modules I'm expecting to get PCBWay or someone to assemble for me.
C2 - CL21A226KOQNNNG. Same series and size, just a different value.
C3 - CC0805JRNPO9BN201. 200pF, because 192pF doesn't seem to be a standard value. NPO temperature curve, 0805 package.
L1 - DFE252012P-1R0M=P2. Stocked by the mega-tonne at Digikey, and ~US$0.30 each, have 4A saturation current, and reasonably low DCR, and acceptable 20% tolerance.
R1 - RN73R1JTTD2913F100. 1% tolerance, which should be enough. It's an 0603, which is a bit fiddlier if you had to hand solder it, but there are no 0805 series in stock at the moment.
R2A - RC0603FR-0791KL. 1% tolerance, but 91K, rather than 92K (turns out 92K is not a real size, after all). This increases the output voltages to 3.36V and 5.05V, which is acceptable.
R3A - RK73H1JTTD1403F 1% tolerance 140K. This brings the 5V output back to 5.01V.
Okay, so that looks like all the parts.
In terms of planning the module dimensions, the IC is ~3-4mm on each edge, and there will need to be 9 passives on there as well, that are ~2x1.25mm for most of them. So the module itself should be able to be quite small in the end. What's also nice, is that all of the components selected are <1.6mm high, and thus should be able to sit in the cut-out of the castellated module without requiring any extra spacing. I'll have to leave that GND buffer around the resistor network as well, which might push things out a bit.
Also, I'm expecting that this module will need to be 4-layer, so that there can be a good ground pad for thermal conduction, as at ~90% efficiency and 2A @ 5V = 10W implies that the DC:DC converter can be dumping as much as 1W as heat, and that needs somewhere to go. It's actually the aspect of this module that worries me the most. But with the strong thermal bonding of the castellated module concept, I'm fairly confident that it will be fine: a short 2.5mm track and solder wick jumper is the only interruption between the ground plane of the module and the ground plane of the carrier board, which will have more than enough thermal capacity to dump that heat.
6. Schematic Design
Okey dokey -- we are now all set to actually design the schematic of this thing.
The passives won't be a problem for KiCad, but as is often the case, the main IC that I need isn't in KiCad's default library, so it's off to SnapEDA to find a footprint and symbol. There is a footprint, but not a symbol, so I'll have to make the symbol. Here's the pinout from the datasheet:
And here's my symbol I've cooked up in the KiCad Symbol editor:
Looks like I've got all the pins right. Good. So let's hook up the reference circuit, but with our feedback circuit using R2A and R2B, and add in the various other things we need here:
There aren't too many surprises here. The only thing I've gone and added is a jumper to force 5V output, if for some reason someone wanted to have that.
So now I guess I need to see how small an area I can layout the PCB, so that I know which size castellated module to use. I'll allow a bit of spare space, so that if the IC has to be swapped for another, it's not a disaster. Here's my first go, without worrying about the GND or VBAT signals that will be routed via internal layers:
So about 13.5 x 23.5mm. But the cut-out in the module can be a bit smaller, as it only needs to allow all the components to fit together. We will need five of these, so I'm inclined to make them as relatively small as I can get away with.
I've just looked at the module footprint sizes I've specified, and they are all too small right now to accommodate this module, so I'll have to make bigger ones. I actually need to update them anyway, to fix the minor issues / potential improvements I identified in a previous blog post. So I guess I'll start on that. This means that the DC:DC module will have way more pads than it needs.
I might purposely under-populate the pins to make soldering/desoldering easier, as well as making it obvious which module goes where -- I fully intend for each module type to have uniquely keyed pin combinations, so that they can't be put in the wrong place without you noticing. This also makes grass-roots assembly much easier, by reducing the number of things you need to look up or know while assembling or repairing.
Most likely it will need to be a 22-pin module to get the necessary length, but not actually any wider than the wide module footprint I have already specified. In fact, they could be a few mm narrower, if necessary. But as mentioned above, we'll keep a bit of spare space, to allow for easier part substitution.
This is what I have so far:
We only need 6 pins, but I've left at least two near each corner, to provide ample strength to hold the module in place. The marked dimensions of the hole are sufficient. So now I need to make the schematic symbol for this. I'll just do one version with all 22 pins for now, as I think it's possible to use a footprint with missing pins, if none of them are connected. If not, then I'll make versions of the symbol as well.
As I'm going to have quite a few possible variants of these larger modules by deleting one or more pins, I've made an identification scheme for the footprints, where -M<hex string> indicates that only some pins are present, with 1s in the hex string corresponding to pins present. For ease of reading the hex, the first hex digits corresponds to pins 1 to 4, with the most significant bit first. So the pattern above is -MA0780C.
Okay, it complains about the missing pads, but still works. Here is what I have so far:
I need to make the board 4-layer and add the VBAT and GND planes, and then in theory, it should be all good. Actually, I think I can keep it 2-layer, with the rear of the board being almost exclusively a GND plane fill, as there is no need for any power planes.
Going through with that, and I've hit an interesting Design Rule Check violation for the footprint for the IC:
A bit of searching found this post about this issue. It looks like for fine-pitched SMD parts you are basically guaranteed to get this violation, and the remedy is to tell the footprint properties that it's okay.
I'm also seeing DRC violations for the castellated pads. Apparently the right way to do these is to let the copper go outside the edge cuts.
Okay, after sorting those out, I have it looking nice now:
But you can also see that I've put URL info and the name of the module on silk-screen on both sides, as well as the revision of the module. This is to make it easier to pick up the right thing, and know whether you can use it.
And the schematic:
So I think this one's ready for sending off for fabrication as soon as someone can do a quick review of the schematic for me, to make sure I haven't done anything stupid.
The KiCad project is here:
https://github.com/gardners/megaphone-r5-modular/tree/main/modules/high-efficiency_dc-dc_converter
Anyone who has feedback can comment on this post, or better yet, file an issue against the repository, even if the feedback is that you don't see any problems, as that's useful information for me, too.
No comments:
Post a Comment