Thursday, February 26, 2015

I haven't blown up my DDR RAM, so that's good

The funny problems I am having with the DDR RAM on the new board, combined with the fact that I accidentally ran the bitstream intended for the non-DDR board had me a bit worried that I had blown up the DDR RAM or some of the pins on the FPGA.

To see if this was the case, I asked the guy who kindly supplied me with my Nexys4 DDR board, and who has one of his own, to test the latest bitstream on his board.  If it booted to the C65 ROM on his, then it would indicate that I have fritzed my DDR RAM, if not, then it would indicate that the problem was with the design, and that I just need to do more work on fixing the problem, without worrying about if the cause was a faulty board.

Here is his board running the bitstream:

And, thankfully, his board behaves just like mine -- so there is nothing wrong with my board.

Now I just have to figure out what is causing the unreliability with the DDR controller interface. 

I have largely taken the example one, but to keep things simple, I am running it on the same 193.75MHz clock that is driving the VIC-IV, instead of the 200MHz clock that was used in the example DDR controller.  I had figured that the small difference would not upset things.  

Now given that it is having problems, and I can't think of any more probable cause, I will take the extra effort to derive a 200MHz clock for the DDR RAM controller.  

Unfortunately, the clock generator I am using can't generate ~192MHz and 200MHz at the same time.  I did think about just pushing the VIC-IV to 200MHz, which would result in 62.5Hz video output, which is not that appealing. It would also put more pressure on the timing closure.

This means I need to figure out how to chain two clock generators, which I have previously not managed to do.  I have so far worked out that I need to remove the global buffers from the front of the clock generators.  What I have yet to work out is if a global buffer will be automatically instantiated and attached to the front of each clock generator. I have it trying to synthesise right now, so we will find out soon enough.

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