Today a parcel arrived in the post containing the updated Nexys4 board, the Nexys 4 DDR. The main difference is the 16MB Cellular RAM is replaced by a 128MB DDR2 RAM, apparently because Digilent can't get the Cellular RAM part any more. The pinouts have changed a little as well. Anyway, because of these changes, I need to slightly tweak the design to work on this new board, which I will hope to do in a couple of weeks time when I finish writing some grants applications for work (which is also why not much has been happening on the project the last few months).
I must also say a big thank you to the supporter who bought this board for me! The generosity is very appreciated. But more than that, it excites me when people support this project, including when someone else provided me with joysticks for testing, as it tells me that a community is growing -- which is what I had hoped.
My German is slowly improving, and so I was able to respond to "Hier offen", upside down, without having to resort to the English cheat text (nur erwarte nicht mich mit dir auf Philosophie noch bereden ;).
As you can see, the board and case are very similar to the old one. The DDR RAM is located below the FPGA. The increased bandwidth of the RAM does open up some new possibilities, but it will be some time before I can explore those. For now, it will just be mapped into the conveniently already almost 128MB (well, 112MB) piece of address space from $8000000-$EFFFFFF. When I finish implementing the 32-bit addressing modes, I will also map it somewhere above 256MB in its entirety.
Very excited about the 65GS. It's just what I've wanted a long time now - a fun, easy, accessible system like the old 8-bits I still love, but something new with greater capabilities to play around with. I can't wait to start programming for it.
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