I have managed to get the DDR RAM on the board almost working.
Sometimes it works fine, and I can write and read back data, and it appears in the correct place in memory.
Other times, all manner of fascinating odd things happen.
Having dug through some information, it looks like I will have to implement temperature compensation between the FPGA and DDR RAM. Basically, as the FPGA, RAM and traces between them change temperature, their electrical properties vary enough to cause problems.
Did I mention that I really don't like DDR memory, because it is too complex? Oh how much nicer it would be if there were cheap 128MB SRAM chips available. If you happen to know of any, I'd love to hear.
Fortunately the FPGA has an internal temperature sensor, and the DDR RAM controller that Digilent and Xilinx provide has an input for the temperature, so that it can recalibrate the communications between the FPGA and the RAM whenever necessary.
I'll take a look at implementing this when I get a chance, and then, hopefully, the C65 ROM will work on the new Nexys4DDR boards.